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LT3710 Secondary Side Synchronous Post Regulator
FEATURES
s s s s s s s s
DESCRIPTIO
Generates a Regulated Auxiliary Output in Isolated DC/DC Converters 0.8V 1.5% Accurate Voltage Reference Dual N-Channel MOSFET Synchronous Drivers High Switching Frequency: Up to 500kHz Programmable Current Limit Protection Programmable Soft-Start Automatic Frequency Synchronization Small 16-Pin Thermally Enhanced TSSOP Package
The LT(R)3710 is a high efficiency step-down switching regulator intended for auxiliary outputs in single secondary winding, multiple output power supplies. The LT3710 drives dual synchronous N-channel MOSFETs and achieves high efficiency. With leading edge modulation, it operates well with either primary side peak current or voltage mode control. It is synchronized to the falling edge of the transformer secondary winding and can be used in both single-ended and double-ended isolated power converter topologies. A high speed operational amplifier is incorporated to achieve optimum compensation and fast transient response. A user selectable discontinuous conduction mode improves light load efficiency. The LT3710 is available in a thermally enhanced TSSOP-16 exposed pad power package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s
48V Isolated DC/DC Converters Multiple Output Supplies Offline Converters
TYPICAL APPLICATIO
VIN 36V TO 72V
L1 VCC BIAS 10k VDD VCC BOOST SYNC GBIAS 10pF LT3710 VFB FG ISNS LTC1698 10k 180pF TG BG LT3781 SG 0.01F CS 680pF CSET TG 0.1F SW ILCOMP BG SS BGS VFB PGND CL- CL+ VAOUT 3.3k 33nF 2.32k 3.01k 220 Q2 B340A 4700pF Q1 L2 1.8H 0.006 4.7F CMDSH-3 VCOMP CG
*
*
*
*
SYNC
OPTODRV VC + - VREF VFB GND
ISOLATION BOUNDARY
COUT2: POSCAP, 680F/4V L2: SUMIDA CEP125-IR8MC-H Q1, Q2: SILICONIX Si7440DP
PLEASE REFER TO FIGURE 3 IN THE APPLICATIONS SECTION FOR THE COMPLETE SCHEMATIC
Figure 1. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
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VOUT1 3.3V AT 10A
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VOUT2 1.8V AT 10A COUT2
3710 F01
1
LT3710
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW BOOST TGATE SW CSET SYNC ILCOMP SS VFB 1 2 3 4 5 6 7 8 17 16 GBIAS 15 BGATE 14 PGND 13 VCC 12 CL- 11 CL+ 10 VAOUT 9 BGS
VCC Supply Voltage .................................................. 26V BOOST Pin Voltage With Respect to SW pin ........... 10V BOOST Pin Voltage With Respect to GND pin .......... 35V SYNC Pin Voltage .................................................... 30V Operating Junction Temperature Range (Notes 2, 3) ...................................... - 40C to 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
Note: If higher than 30V on SYNC pin is needed, add a 10k resistor in series with the pin.
ORDER PART NUMBER LT3710EFE
FE PART MARKING 3710EFE
FE PACKAGE 16-LEAD PLASTIC TSSOP
TJMAX = 125C, JA = 38C/W EXPOSED PAD IS SGND (PIN 17) MUST BE CONNECTED TO PGND AND SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs unless otherwise noted.
PARAMETER Overall Supply Voltage (VCC) Supply Current (IVCC) Boost Pin Current VAOUT 1.2V (Switching Off) VBOOST = VSW + 8V, 0V VSW 24V TGATE High TGATE Low 0.788 0.780
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 8
TYP
MAX 24
UNITS V mA mA mA V V A V V
7 2 2 0.8 0.2 4.5 0.8
q
12 3 3 0.812 0.820 0.5
Voltage Amplifier VA Reference Voltage (VREF)
q
FB Pin Input Current VAOUT High VAOUT Low VAOUT Source Current Open-Loop Gain Gain Bandwidth Product Soft-Start Current Current Limit Amplifier CA1 Current Limit Threshold at (VCL+ - VCL-) BGATE Off Threshold at (VCL+ - VCL-), BGS Pin Float Switching Off Threshold at ILCOMP Input Current (CL+, CL-)
VFB = VREF
100 100 10 5 12 70 8 100
300
18 85 15 0.15
Common Mode Voltage from 0V to VCC - 2.5V Common Mode Voltage from 0V to VCC - 2.5V VILCOMP VCL+ = VCL-
q
50 0
2
U
A dB MHz A mV mV V A
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LT3710
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs unless otherwise noted.
PARAMETER Oscillator Switching Frequency Synchronization Frequency Range CSET Ramp Valley Voltage CSET Peak-to-Peak Voltage Synchronization Pulse Threshold on SYNC Pin Maximum Duty Cycle Gate Drivers (TGATE, BGATE) VGBIAS VTGATE High (VTGATE - VSW) VBGATE High VTGATE Low (VTGATE - VSW) VBGATE Low Peak Gate Drive Current Gate Drive Rise and Fall Time IGBIAS < 25mA ITGATE < 50mA, VBOOST = VGBIAS - 0.5V IBGATE < 50mA ITGATE < - 50mA IBGATE < - 50mA 10nF Load 1nF Load
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS CS = 500pF (No SYNC) CS = 333pF (No SYNC) CS = 500pF CS = 333pF CS = 1000pF (No SYNC) CS = 1000pF (No SYNC) Falling Edge VSYNC VFB = VREF - 5mV, CS > 500pF
q q q q q
MIN 170 240 245 345 0.90
TYP 200 280
MAX 240 340 400 500
UNITS kHz kHz kHz kHz V V V %
1.15 2.4 2.5
1.4
85 7.5 5 5
90 8.0 6 6 8.5 7 7.5 0.5 0.5 1 25
V V V V V A ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3710E is guaranteed to meet performance specifications from 0C to 125C. Specifications over the - 40C to 125C operating temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFOR A CE CHARACTERISTICS
VGBIAS vs IGBIAS over Junction Temperature
8.1 -40C 12 8.0
VGBIAS (V)
25C
ICC (mA)
GAIN (dB)
7.9
7.8 125C 7.7 0 10 IGBIAS (mA) 20 26
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UW
ICC vs VCC (Switching Off)
13 TA = 25C 120
Voltage Amplifier VA Gain and Phase
TA = 25C GAIN (-111) PHASE 40 -100 -0
11 10 9 8 7 6 5 8 10 12 14 16 18 VCC (V) 20 22 24
80
-50 PHASE (DEG)
0 0dB, 10MHz -20 10 100 1k 10k 100k 1M FREQUENCY (Hz)
-150 -180 10M 100M
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3710 G02
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LT3710 TYPICAL PERFOR A CE CHARACTERISTICS
VREF vs VCC, FREQ vs VCC
CSET = 500pF 3 TA = 25C
VREF (mV)
2 1 0 -1 FREQ 1 0 -1 10 15 VCC (V) 20 25
3710 G04
VREF (V)
VREF
Frequency vs Temperature
195 SWITCHING FREQUENCY (kHz) CSET = 500pF 500
200
FREQUENCY (kHz)
205
210
215 -40
-20 0 25 50 75 JUNCTION TEMPERATURE (C)
GBIAS vs IGBIAS (Charging 2.2F)
8 CGBIAS = 2.2F 300 250 200 150
IGBIAS (mA)
VAOUT (V)
100 50 0 0 500s TIME IGBIAS
4
UW
VREF vs Temperature
0.801 CSET = 500pF
0.800
FREQ (kHz)
0.799
0.798 -40
-20 0 25 50 75 JUNCTION TEMPERATURE (C)
125
3710 G05
CSET vs Switching Frequency
TA = 25C 1.00 CSET 400 0.95 MAXIMUM DUTY CYCLE 0.90 300 0.85 0.80 200 0.75 0.70 125
3710 G06
MAXIMUM DUTY CYCLE
100 200
400
600 CSET (pF)
800
1000
3710 G07
Current Limit Amplifier CA1 Gain at VCC = 11V, VCL- = 5V
12 VCC = 11V 7 VCLN = 5V TA = 25C 6 5 4 3 2 CSET VALLEY 0 1ms 1 0 50 60 70 80 VCL+ - VCL- (mV) 90
3710 G09
VGBIAS
10 8
VGBIAS (V)
6 4 2
CSET PEAK
3710 G08
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LT3710
PI FU CTIO S
BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin is used to bootstrap and supply the topside power switch gate drive circuitry. In normal operation VBOOST is powered from the internally generated 8V GBIAS, VBOOST = VSW + 8.2V when TGATE is on. TGATE (Pin 2): Topside (Boosted) N-Channel MOSFET Driver. When TGATE is on, the voltage is equal to VSW + 6V. SW (Pin 3): Switch Node Connection to Inductor. CSET (Pin 4): Oscillator Timing Pin. The capacitor on this pin sets the PWM switching frequency. SYNC (Pin 5): Synchronization Input. This pin should be connected to the secondary side output of the power transformer with a series resistor. A filtering capacitor of 10pF is recommended. ILCOMP (Pin 6): Current Limit Amplifier Compensation Node. At current limit, CA1 pulls down on this pin to regulate the output current. SS (Pin 7): Soft-Start. A capacitor on this pin sets the output ramp up rate. The typical time for SS to reach the programmed level is (C * 0.8V)/10A. VFB (Pin 8): Voltage Amplifier Inverting Input. A resistor divider to this pin sets the output voltage. Nominal voltage at this pin is 0.8V. BGS (Pin 9): Bottom Gate Switching Control. CA2 monitors the inductor current and prohibits BGATE from turning on when the inductor current is low (below 8mV across the current sense resistor RS1) to allow discontinous mode operation. Grounding this pin disables comparator CA2. VAOUT (Pin 10): Voltage Amplifier Output. CL+ (Pin 11): Current Limit Amplifier Positive Input. The threshold is set at 70mV. CL- (Pin 12): Current Limit Amplifier Negative Input. When used, CL- is connected to the output capacitor side of the current + sense resistor and CL+ is connected to the inductor side of the current sense resistor. VCC (Pin 13): Supply of the IC. For proper bypassing, a low ESR capacitor is required. PGND (Pin 14): Ground of the Bottom Side N-Channel MOSFET Driver. BGATE (Pin 15): Bottom Side N-Channel MOSFET Driver. GBIAS (Pin 16): 8V Regulator Output for Boostrapping VBOOST . A bypass capacitor of at least 2F is needed. Exposed Pad (Pin 17): Connect to PGND (Pin 14).
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LT3710
BLOCK DIAGRA
2.5V 16 C3 2F C2 0.3F A8
+ - +
7V A10 8V
C4 2nF R3 R4
VOUT2 COUT 100F
SW
- +
+
+
3.5V R A5 RESET SS 2V A11 I2 200A 9 BGS CL+ 11 PWM CA2 A7 14 PGND 15 R2 BGATE S A6 M2
+ -
+
1.6V
SYNC
+
- + - +
OSC 8mV A1 ONE SHOT
RS 10k
5
- -
CA1 D5
12
CL-
CS 10pF A2
E4
+ +
70mV
+ +
2.5V
6
ILCOMP R6 5k 10 VAOUT C6 100pF
CSET
4
C5 500pF D6
-
VA D7
8
VFB
R5 2k C1 500pF
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+
I1 10A 5V 7 SS C7 5nF D4
VREF 0.8V
SGND
NOTE: EXPOSED PAD (PIN 17) IS SGND AND MUST BE CONNECTED TO PGND (PIN 14).
17
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6
1 BOOST
VS
R7
D1
R8
Q1 VCC
13 E2 SHUTDOWN A4 BGATE 8V L1 RS1 GBIAS D3 IL A3 3 SW IO 2 R1 M1 TGATE
- + + + + -
C8 2F
D2
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LT3710
OPERATIO
To generate isolated multiple outputs, most systems use either multiple secondary windings or cascade regulators for each additional output. Multiple secondary windings sacrifice regulation of the auxiliary outputs. Cascaded regulators require a larger inductor for the main output, because all of the power is processed in series. By generating the auxiliary output(s) from the secondary winding of the main output, the LT3710 allows for parallel processing of the output power. This minimizes the main output inductor size and directly regulates the auxiliary output. With synchronous rectification, the system efficiency is greatly improved. Refering to the Block Diagram, the LT3710 basic functions include a voltage amplifier, VA, to regulate the output voltage to within typically 1.5%, a voltage mode PWM with trailing edge synchronization and leading edge modulation, a current limit amplifier, CA1, and high speed synchronous switch drivers. During normal operation (see Figure 2), a switching cycle begins at the falling edge of the transformer secondary voltage VS. The internal oscillator is reset, turning off the top MOSFET M1 and turning on the bottom MOSFET M2. During this portion of the cycle, the inductor current is discharged by the output voltage VOUT2. The transformer secondary voltage VS will go high during this portion of the cycle. Since M1 is off, the switch node voltage VSW remains zero. The inductor current continues to be discharged by the output voltage VOUT2. This condition lasts
APPLICATIO S I FOR ATIO
Synchronization and Oscillation Frequency Setting The switching is synchronized to the secondary winding falling edge and the synchronization threshold is typically 2.5V. The synchronization falling edge triggers an internal inverted ramp (see Figure 2) and starts a new switching cycle for the leading edge voltage mode PWM. The reason for using leading edge modulation is to keep the transformer primary side peak current sensing undisturbed. For proper synchronization, the oscillator frequency should be set lower than the system switching frequency with tolerances taken into account.
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until the ramp signal intersects the feedback error amplifier output VAOUT. The top MOSFET M1 turns on, pulling the switch node voltage to VS. The inductor current of the LT3710 circuit is then charged by VS - VOUT2. The effective on time of this buck circuit ends when the secondary voltage becomes zero. The next cycle repeats. The ideal equation for duty cycle of the LT3710 is: D2 = VOUT2/VSP where VOUT2 is the auxiliary output voltage, VSP is the amplitude of the secondary voltage and D2 is the duty cycle of the switching node voltage VSW, as defined in Figure 2.
VRESET T D1T TRANSFORMER SECONDARY VOLTAGE SYNC SIGNAL VRESET VS VSP RAMP VCSET VAOUT TGATE BGATE IL T SWITCH NODE VSW D2 T VSP
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Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
fOSC < (fSL * 0.8) fSL is the low limit of the system switching frequency and 0.8 is the tolerance of fOSC. For example, a system of 200KHz with 15% tolerance, then fSL = 200k * 85% = 170kHz; and fOSC < (170k * 0.8), fOSC should be set below 136kHz. Once fOSC is determined, CSET can be calculated by CSET = (107250pf/fOSC(kHz)) - 50pF. For fOSC = 100kHz, CSET = 1022.5pF.
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LT3710
APPLICATIO S I FOR ATIO
Output N-Channel MOSFET Drivers The LT3710 employs high speed N-channel MOSFET synchronous drivers to achieve high system efficiency. GBIAS is the 8V regulator output to bias and supply the drivers and should be properly bypassed with a low ESR capacitor to ground plane. A Schottky catch diode is required on the switch node. Light Load Operation If the BGS pin is grounded, the LT3710 stays in continuous mode independent of load condition except in soft-start operation (see Soft-Start section). If the BGS pin is left open, under light load and VRS1 drops below 8mV, BGATE will be turned off(see comparator CA2 of Block Diagram) and the LT3710 goes into discontinous mode operation. Current Limit Current limit is set by the 70mV threshold across CL+ and CL -, the inputs of the amplifier CA1. By connecting an external resistor RS1(see Block Diagram), the current limit is set for 70mV/RS1. R6 and C6 stablize the current limit loop. If current limit is not used, both CL+ and CL - should be grounded and the BGS pin should also be grounded to disable comparator CA2. Soft-Start and Shutdown During soft-start, VSS is the reference voltage that controls the output voltage and the output ramps up following VSS. The effective range of VSS is from 0V to VREF. The typical time for the output to reach the programmed level is (C * 0.8V)/10A. During start up, BGATE will stay off until VSS gets up to 1.6V. This prevents the bottom MOSFET from turning on if the output is precharged. To shut down the LT3710, the SS pin should be pulled below 50mV by a VN2222 type N-channel transistor. Note that during shutdown BGATE will be locked off when VSS drops below 0.6V. This prevents the bottom MOSFET from
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discharging the output, which would cause the output to undershoot below ground. Layout Considerations For maximum efficiency, the switching rise and fall times are less than 20ns. To prevent radiation, the power MOSFETs, SW pin and input bypass capacitor leads should be kept as short as possible. A ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. Note that the bottom metal of the package is the heat sink, as well as the IC signal ground, and must be soldered to the ground plane. Output Voltage Programming The feedback reference voltage is 0.8V. The output voltage can be easily programmed by the resistor divider, R3 and R4, as shown in the Block Diagram. R3 VOUT2 = 0.8 * 1 + R4 Filtering on the SYNC Input It is necessary to add RC filtering on the SYNC input of the LT3710 to eliminate the negative glitch at the turn on of the top MOSFET. When the top MOSFET M1 turns on, the transformer secondary current instantly changes from the original first output inductor current to the sum of two output inductor currents. The high di/dt on the transformer leakage inductance causes the transformer secondary voltage VS to drop for a short interval. If the leakage inductance is large enough, the VS dip will be lower than the synchronization threshold (about 2.5V), falsely triggering the synchronization. The top MOSFET is turned off immediately. As a result, the output voltage will not be regulated properly. A filter circuit is needed to ensure proper operation. A small RC filter with RS = 10k and CS = 10pF are typical.
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LT3710
APPLICATIO S I FOR ATIO
Output Inductor Selection The key parameters for choosing the inductor include inductance, RMS and saturation current ratings and DCR. The inductance must be selected to achieve a reasonable value of ripple current, which is determined by:
VOUT2 * (1 - D2) IL = f *L
Typically, the inductor ripple current is designed to be 20% to 40% of the maximum output current. The RMS current rating must be high enough to deliver the maximum output current. A sufficient saturation current rating should prevent the inductor core from saturating. These two current ratings can be determined by:
ILMAX2 IRMS IO + 12 I ISAT IO + LMAX 2
2
where IO is the maximum output current and ILMAX is the maximum peak-to-peak inductor ripple current. To optimize the efficiency, we usually choose the inductor with the minimum DCR if the inductance and current ratings are the same. Power MOSFET Selection The LT3710 drives two external N-channel MOSFETs to deliver high currents at high efficiency. The gate drive voltage is typically 6.5V. The key parameters for choosing MOSFETs include drain to source voltage rating VDSS and RDS(ON) at 6.5V gate drive. Note that the transformer secondary voltage waveform will overshoot at its rising edge due to the ringing between transformer leakage inductance and parasitic capacitance. The VDSS of both top and bottom MOSFETs must be sufficiently higher than the maximum overshoot. It is recommended that an RC snubber or a voltage clamping circuitry be placed across the transformer secondary winding to limit the VS overshoot.
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The RDS(ON) of the MOSFETs should be selected to deliver the required current at the desired efficiency as well as to meet the thermal requirement of the MOSFET package. The conduction power losses of the MOSFETs are: PM1 IO2 * RDS(ON)M1 * D2 PM2 IO2 * RDS(ON)M2 * (1 - D2) where IO is the maximum output current of LT3710 circuit, RDS(ON)M1 and RDS(ON)M2 are the on-resistance for the top and bottom MOSFETs, respectively. The RDS(ON) must be determined with 6.5V gate drive and the expected operating temperature. A good number of high performance power MOSFET selections are available from Siliconix, International Rectifier and Fairchild. If the VDSS and RDS(ON) ratings are the same, the MOSFETs with the lowest gate charge QG should be chosen to minimize the power loss associated with the MOSFET gate drives, the switching transitions and the controller bias supply. Output Capacitor Selection The selection of the output capacitor is determined by the output ripple and load transient requirements. In low output voltage applications, always choose capacitors with low ESR. The output ripple voltage is approximated by:
1 VOUT IL ESR + 8fC OUT
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where IL is the inductor peak-to-peak ripple current. A partial list of low ESR high performance capacitor types includes SP capacitors from Panasonic and Cornell Dubilier, POSCAPs and OS-CON capacitors from Sanyo, T510 and T520 surface mount capacitors from Kemet. Design Example Figure 3 shows an application example for the LT3710. It is a dual output, high efficiency, isolated DC/DC power supply with 36V to 72V input, 3.3V/10A and 1.8V/10A outputs. The basic power stage topology is a 2-transistor
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LT3710
*
VIN-
*
2 10 Si7440DP 4
5
1nF 100V
1F
470F 4V POSCAP
*
Q2 0.025 1/2W 3 B0540W 2.2nF 250VAC B0540W
Si7440DP x2
VOUT RTN
330pF FZT690B 4.7F CMPZ5240B 10V
VCCS
2k
0.22F
BAT54
20k
FZT 853 ZVN3310F BAT54 1F BAS21 BAT54 BAS21 20 TG BSTREF BG SENSE LT3781 FSET 3 8 3k 3.3nF 10 7 4 7 6 5 8 1k VOUT1 2 0.01F THERM SYNC SGND SS VC VFB 9 5VREF PGND 12 SG 1* 43 3.3 0.1F 0.1F 19 18 15 11 14 4 7 220pF T2 PULSE P2033 1 4.7k 15 SYNC 1k 1 4.7nF 14 10 82pF 4.7nF 5 OPTODRV LTC1698 12 11 16 2 22nF 470 6 VDD ISNS ISNSGND FG CG VCOMP VFB OVPIN MARGIN VAUX PGND GND PWRGD ICOMP 3 0.1F 4 10 8 9 7 13 1.24k 1%
3710 F03a
11V MMSZ5241B
10k
B0540W
1nF
DO1608C-105
NOTE UNLESS NOTED: ALL CAPS 25V ALL RESISTORS 0.1W, 5% Q1, Q2 SILICONIX Si7456DP
73.2k
270k
BAS21
13
VCC VBST
2
*8
2.43k 1%
3.01k 1%
OVLO
1 5 6 52.3k 1%
1N4148
SHDN 5VREF
1.78k 1% VOUT1 TRIM
ON/OFF
10k
5VREF
0.1F
1nF
1F
4.7F
1.24k
Figure 3a. 36V to 72V DC to 3.3V/10A and 1.8V/10A (or 2.5V/10A) Dual Output Isolated Power Supply-Basic Circuit (Part 1 of 2, See Next Page)
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APPLICATIO S I FOR ATIO
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SEC VOUT1+ 3.3V AT 10A 2.5H SUMIDA CEP125-2R5 1.5F 100V Q1 10 7 MUR120S MUR120S 1nF 100V 470F 4V POSCAP T1 PULSE PA0191 1
1.2H COILCRAFT D01813P-122HC
VIN+
1.5F 100V
+ +
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LT3710
APPLICATIO S I FOR ATIO
forward converter with synchronous rectification. The primary side controller uses an LT3781, a current mode 2-transistor forward controller with built-in MOSFET drivers. On the secondary side, an LTC1698 is used to provide the voltage feedback for the 3.3V output, as well as the gate drive for the synchronous MOSFETs. The error amplifier output is fed into the optocoupler and then relayed to LT3781 on the primary side to complete the 3.3V regulation. The 1.8V output is generated by the LT3710 circuit. A planar transformer PA0191 built by Pulse Engineering is employed as the power transformer in this design. This transformer is constructed on a PQ20 core with a nine turn primary winding, two turn secondary winding and seven turn auxiliary winding for the LT3781 bias supply. Because
10pF 10k SEC 0.01F VCCS 1F C37 680pF 5 7 13 4 14 6 180pF 10k 17 SYNC SS VCC CSET PGND ILCOMP PGND VAOUT 10 0.033F
1 BOOST
4.7F 16V CMDSH-3 GBIAS TGATE SW BGATE BGS CL+ VFB 8 3.3k 16 2 3 15 9 11
LT3710
12 CL- 0.01F 4700pF 3.01k 1% 220
330pF
Figure 3b. 36V to 72V DC to 3.3V/10A and 1.8V/10A Dual Output Isolated Power Supply (Part 2 of 2, See Previous Page)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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the maximum secondary voltage VSP is about 16V, 30V MOSFETs are chosen with the consideration that the secondary voltage overshoot is typically 20% to 30% of VSP. In this particular design, Si7440DP is selected due to its low RSD(ON), 30V VDSS rating and its compact and thermally enhanced PowerPak SO-8 package. The switching frequency of the circuit is about 230kHz. 1500V input to output isolation is provided. Additional features of this design include primary side on/off control, 5% secondary side trimming on the 3.3V output, input overvoltage protection and undervoltage lockout. The complete design will mount within a standard half brick PC board with about half inch height.
0.1F 16V Si7440DP 10 1.8H SUMIDA 0.006 CEP125-IR8 1% Si7440DP B340A CMDSH-3
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680F 4V POSCAP
+
VOUT2 1.8V/10A 680F 4V POSCAP
2.32k 1%
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LT3710
PACKAGE DESCRIPTIO U
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
2.74 (.108) 4.90 - 5.10* (.193 - .201) 2.74 (.108) 16 1514 13 12 1110 6.60 0.10 4.50 0.10 SEE NOTE 4 0.45 0.05 1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0 - 8 12345678 1.10 (.0433) MAX 9
2.74 (.108) 2.74 6.40 (.108) BSC
0.09 - 0.20 (.0036 - .0079)
0.45 - 0.75 (.018 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118)
0.05 - 0.15 (.002 - .006)
FE16 (BA) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
RELATED PARTS
PART NUMBER LT1339 LT1425 LT1431 LT1680 LT3781 LT1725 LT1737 LT1950 LT3804 DESCRIPTION High Power Synchronous DC/DC Controller Isolated Flyback Switching Regulator Programmable Reference High Power DC/DC Step-Up Controller Dual Transistor Synchronous Forward Controller General Purpose Isolated Flyback Controller High Power Isolated Flyback Controller PWM Controller for Flyback, Forward and SEPIC Applications Secondary Side Dual Output Controller with Optodriver COMMENTS Operation Up to 60V Maximum General Purpose with External Application Resistor 0.4% Initial Voltage Tolerance Operation Up to 60V Maximum Operation Up to 72V Maximum Drives External Power MOSFET with External ISENSE Resistor Sense Output Voltage Directly from Primary-Side Winding 15W to 500W, Isolated and Nonisolated Power Supply 50% Smaller Transformer, Protects MOSFET Regulates Two Outputs, Optocoupler Feedback Driver and Second Output Synchronous Driver Controller
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0803 1K * PRINTED IN USA
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(c) LINEAR TECHNOLOGY CORPORATION 2002

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Price & Availability of LT3710EFE

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